Analog-to-digital converters employing continuous-time chaotic internal circuits to maximize resolution-bandwidth product—CT TurboADC

ABSTRACT

An analog-to-digital conversion devices and methods that approach a linear relationship between resolution and oversampling rate. The process involves modulating an input analog signals with an essentially chaotic encoding signal that is deterministic, aperiodic in that it lacks spectral tones above a threshold, and bounded. The resulting encoded signal is quantized into a bit stream and decoded by applying to that bit stream a non-linear estimation related to said chaotic signal to thereby produce an output representing said input analog signal in digital form.

CROSS-REFERENCE TO PRIOR APPLICATIONS

The patent application claims the priority to and incorporates byreference the entire content of provisional application 62/739,891 filedOct. 4, 2019.

TECHNICAL FIELD

This patent application pertains to apparatuses and methods foranalog-to-digital conversion of electrical signals, and moreparticularly, to apparatuses and methods for performing a high-speed andhigh-resolution conversion of analog electrical signals to digitalformat.

BACKGROUND

Much if not most real-world information originates in analog form andmust be converted to digital for processing and use. Analog-to-digitalconverters (ADC) and conversion methods have experienced rapid growth inrecent decades due to the steady development of CMOS technologies andthe increasing demand for higher resolution and bandwidth. See thereferences that are listed at the end of the Detailed Descriptionportion of this patent application and are identified by referencenumeral in square brackets in the discussion below. All are incorporatedby reference in this patent specification. CMOS technologies haveallowed more systems (both analog and digital) to be integrated into asingle chip, thus reducing manufacturing costs and allowing additionalfunctions such as calibration techniques.

There are two mainstream ADC techniques: Nyquist rate ADCs (e.g., Flash,Single-slope, Dual-slope, SAR, and Cyclic) and oversampling ADCs (e.g.,oversampling PCM and ΔΣ converters). Nyquist rate ADCs are commonly usedfor low-to-moderate precision (resolution) and high bandwidth conversionapplications, as seen in FIG. 1. Their resolution is limited by twofundamental sources of noise, thermal and flicker noise, as well ascircuit imperfections such as DC offsets and non-linearity. ΔΣ ADCs areused for high-precision low-to-moderate bandwidth applications. Theirbandwidth is limited by the oversampling demands and the precision islimited by circuit noise and to a lesser extent by non-idealities suchas DC offset, gain error, and non-linearity. In addition, ΔΣ ADCs areprone to instability due to the presence of a non-linear comparisonoperation within a feedback loop, which limits the order of ΔΣ ADCs inpractical implementations. An overview ΔΣ ADC principles andstate-of-the-art is provided in [9]-[11]. More recently, novel ADCmethods have been introduced that rely heavily on joint-processing ofdigital samples to increase the RBW and decrease the complexity ofanalog components [4]-[8]. However, no single ADC method is known to beable to cover the full breath of potential applications (starting fromlow-power conversions for bio-sensing and IoT applications to high-speeddirect RF conversion in radar and communications).

The many known types of ADCs employ different trade-offs of speed, cost,resolution, and other properties. A typical characteristic they share isthat cost and complexity increase nearly exponentially with an increaseof a property such as conversion speed or resolution.

A surprising result described in [12] is the discovery that the limitingresolution of an ADC can be proportional to the oversampling-ratio(OSR), as opposed to widely-held beliefs that the resolution isproportional to log₂(OSR), a dramatic increase in the achievableresolution. This result, which resembles Shannon's result for thecapacity of a communication channel, represents a paradigm shift inunderstanding of data conversion methods and provides encouragement thatnew methods may be found. To achieve this theoretical limit, theinternal analog modulator (or filter) of an ADC should be a chaoticsystem, so that small as well as large changes in the input signal causelarge (but bounded) deterministic changes at the output of themodulator—in some ways similar to the “Butterfly effect”.

SUMMARY

The present invention provides a new class of ADC's, called hereincontinuous-time (CT) TurboADC's, that can trade off resolution forbandwidth on the fly, keeping their product equal to or at least closeto the fundamental information theoretic limit. These designs imposemodest requirements on the analog front-end resources and power at theexpense of somewhat greater complexity in the back-end decoder. Acontinuous-time TurboADC described in this patent application can beconceptualized as a hybrid between a continuous-time Delta-Sigma (ΔΣ)modulator and a Cyclic ADC, with the best features of bothdesigns—oversampling, noise shaping, and simplicity from the Sigma-deltaADC approach and fast half-interval searching from Cyclic ADC's. In oneaspect, the present invention provides an analog-to-digital converter(ADC), comprising: a port for an input analog signal; a sourceconfigured to provide a continuous-time chaotic encoding signal that isdeterministic, aperiodic above a threshold, and bounded; an encoderconfigured to encode said input analog signal with said chaotic signalto thereby produce an encoded analog signal; a quantizing circuitconfigured to quantize said encoded analog signal into a bit stream; anda decoder configured to apply to said bit stream a non-linear estimationrelated to said chaotic signal to thereby produce an output representingsaid input analog signal in digital form; wherein aperiodic above athreshold refers to lacking spectral tones above a threshold. In anotherembodiment, the input analog signal is sampled at an oversampling rate(OSR). In one embodiment, the output signal from the CT TurboADC has aresolution R proportional to OSR and varies linearly with a bandwidth ofthe ADC. In another embodiment, the chaotic encoding signal is generatedby a chaotic oscillator based on negative-Gm LC-tank oscillator. Inanother embodiment, the chaotic encoding signal is generated by acontinuous-time chaotic Chua circuit. In another embodiment, the decoderproducing an output representing said input analog signal in digitalform is implemented as a neural-network.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates TurboADC design space where data points showeffective resolution vs. Nyquist rate of existing ADC methods includingswitched-capacitor ΔΣ (SDDT), continuous-time ΔΣ (SDCT), SAR and CyclicADC, assuming that the maximum sampling rate of CT TurboADC is close to9 GHz, as in [3].

FIG. 2 illustrates an analog-to-digital converter as a communicationsystem.

FIGS. 3(a) and 3(b) show 1-dimensional chaotic maps, where 3(a) shows atraditional Bernoulli map and FIG. 3(b) shows a modified Bernoulli mapas an analog encoder, as described in [12].

FIG. 4 is a block schematic of a DT TurboADC employing modifiedBernoulli chaotic map, as described in [12].

FIG. 5 illustrates one embodiment of continuous-time TurboADCimplementing an -Gm LC tank chaotic oscillator.

FIG. 6 illustrates another embodiment of the continuous-time TurboADCemploying Chua type chaotic circuit driven by an input analog signalV_(in)(t), whose state is compared by a comparator against a thresholdand the resulting output (bit stream y[n]) is provided to a non-lineardecoder implemented as a recurrent neural-network to generate amulti-bit digital representation of the input analog signal. Theembodiment includes an optional comparator that determines the polarityof the input analog signal V_(in)(t), and provides this additionalinformation to the non-linear decoder for faster convergence. Chua diodeshown in this figure is an important active component of a Chua typechaotic circuit exhibiting a piece-wise-linear current-voltagecharacteristic necessary to establish chaotic behavior (see [16] fordetails on Chua diode).

DETAILED DESCRIPTION

A synergy of two distinct fields (Information theory on one side and theprinciples and methods of A/D conversion on the other) has led to amathematical framework that, among other things, helped derivefundamental theoretical limits on the resolution-bandwidth product ofAnalog-to-digital converters (ADC) and also helped prove essential andoften unexpected results [12]. For example, it is traditionally assumedthat the quantization noise in ADCs is independent of the input analogsignal. As a direct consequence to this assumption, the effective numberof bits (ENOB) or resolution is always proportional to log₂ (OSR), wherethe OSR is the oversampling ratio. By using Information theory tools, ithas been discovered that this assumption is fundamentally flawed, andthat the quantization noise is instead fully dependent on the inputanalog signal because its entropy is zero given the input analog signal,so that the resolution can be instead proportional to OSR. Thisrepresents a paradigm shift in understanding A/D conversion methods andleads to novel methods of conversion. This patent specificationintroduces a novel class of ADC, termed Continuous-Time TurboADC (CTTurboADC), that can trade resolution and bandwidth on the fly whilepreserving their product constant and equal or nearly equal to thefundamental theoretical limit with minimal use of analog front-endresources and power. Thanks to their simple front-end design (as simpleas the 1st order ΔΣ modulator) and ease of integration, the CT TurboADCsdescribed in the patent specification can replace many traditional ADCmethods and even enable new applications such as software defined radio,direct RF signal conversion in communications, radar, ultrasound, andMRI imaging systems.

FIG. 1 illustrates a design space and how TurboADCs fit in. The datapoints represent effective resolution vs. bandwidth for more than 200traditional ADC designs including Successive Approximation (SA), Cyclic,Discrete-time (SDDT) and Continuous-time (SDCT) ΔΣ ADC, [1]. Designsthat include pipelining, time-interleaving, and other means ofparallelism (such as Flash ADC) are omitted for fair comparison due totheir much-increased complexity, area, and power. This figure also showsupper bounds on resolution-bandwidth (RBW) product imposed by aperturejitter (for 100 fs and 10 fs RMS jitter), thermal noise corresponding tonoise equivalent resistance of 50Ω, and Heisenberg uncertainty principleas derived in [10]. It also shows upper bounds imposed by quantizationnoise (QN) according to our theory in [13]. Our vision is that theentire design space could be encompassed by discrete-time (DT) TurboADCfor high-resolution and medium speed as described in [12], and our novelcontinuous-time (CT) TurboADC for high-speed conversion as described inthis patent application, and finally a Photonic TurboADC for ultra-highconversion speeds in hundreds of GS/sec, as shown in FIG. 1.

An ADC could be described as a communication system, as shown in FIG. 2.The information source is analog, meaning it provides a continuous-timeand continuous amplitude signal such as voltage, current, or charge tothe ADC. The analog signal is either sampled at a certain sampling ratef_(s) and the samples V_(in)[nT_(s)] are fed to the discrete-time analogfilters and amplifiers of the ADC, or it is fed to the internal circuitsof the ADC as a continuous-time signal V_(in)(t) (e.g., Continuous-timeΔΣ ADCs). The amplifier/filter structures process the analog signal byperforming a form of encoding before the signal enters the comparator,which plays the role of the ‘noisy’ channel. The output from thecomparator generated at the rate of f_(c) is then decoded by digitalcircuitry and usually fed back to the encoder. In general, the ratef_(c) at which the comparator is operating is either equal to f_(s)(such as in ΔΣ ADCs) or larger (such as in SAR and Cyclic ADCs). Infact, for almost every ADC method, a correspondingforward-error-correction (FEC) code can be found. For example, the SARADCs correspond to a form of block code with channel feedback. The ΔΣADCs correspond to convolutional codes, where the ΔΣ modulator acts as aconvolutional encoder and its decimation filter plays the role of themaximum likelihood decoder. Also, the order of the ΔΣ modulator definesthe memory length of the encoder. Describing an ADC as a communicationsystem with FEC coding involves the assumption that the comparator(s) ofan ADC is a ‘channel’ since it injects quantization noise into the‘transmitted’ signal even if the circuit components are otherwisenoiseless. Once the comparator of the ADC is described as acommunication channel, its intrinsic capacity (i.e., maximum number ofinformation bits that can be digitized per second) can be derived. Sincethe QN is neither Gaussian nor independent of the input signal to thecomparator (in fact, the QN in an ideal ADC system is fully describedgiven the input signal), the Shannon capacity formula C=B*log₂(1+SNR),where B is the channel bandwidth, as derived in [2], cannot be appliedto calculate the capacity of such a system. A more general approachinvolving mutual information and entropy should be used. Some importantconclusions from previous work about ADC theory are listed below in theform of theorems (for proofs see [12] and [13]).

Theorem 1. Capacity: Maximum information rate at the output of an ADCemploying M comparators operated at f_(c) comparisons per second isequal to M*f_(c) bits per second. This maximum information rate isdefined as a Conversion Capacity C_(ADC).

Theorem 2. Existence: There exists at least one ADC that can operate atthe C_(ADC) regardless of the input signal statistics. This type of ADCis termed TurboADC with reference to Turbo codes in communications thatare able to approach Shannon's channel capacity.

Theorem 3. Necessary condition: An ADC can achieve the conversioncapacity if the autocorrelation function of the input to its internalcomparator(s) is a delta function (i.e., white spectral properties)regardless of the input signal statistics.

Consequently, two properties of a TurboADC can be derived.

Corollary 1. The internal analog filter of a TurboADC that encodes theinput signal before it is fed to the comparator, must be a non-linearfilter (or a non-linear mapping).

Corollary 2. The output of the comparator in a TurboADC is a sequence ofindependent uniformly distributed bits.

Theorem 4. Oversampling: If an ADC operates at its capacity and theinput analog signal is oversampled by a factor of OSR=f_(c)/2f_(in), theeffective resolution in the baseband is equal to OSR bits.

Perhaps the most interesting and unexpected property of a TurboADC isthe one described in Theorem 4. It states that the resolution of aTurboADC is proportional to the OSR. In contrast, traditionaloversampling ΔΣ ADC's achieve effective resolution that is proportionalto log₂(OSR). Clearly, for the same resolution, a TurboADC may operateat an exponentially lower sampling rate than the ΔΣ ADC's. Also, fromTheorem 4 flows a conclusion that resolution of a TurboADC tradeslinearly with its bandwidth such that the R-BW product is constant andequal to C_(ADC). For example, to increase the resolution from 8 to 16bits, a 2nd-order ΔΣ ADC would have to increase its sampling rate by afactor of 9.1 while a TurboADC would only have to double it (5 timesreduction in power), which could prove crucial in battery-operated IoTdevices. On the other hand, for the same technology node and powerconsumption, TurboADC may achieve data rates significantly higher thanother ADC methods, which may enable new high-speed conversionapplications. Finally, from Theorems 1 and 3 we prove the followingtheorem.

Theorem 5. Chaotic encoder: In order to achieve the theoretical limit tothe R-BW product (the capacity) irrespective of the input signalstatistics, the ADC's internal analog filter should be a deterministicsystem with aperiodic and bounded state trajectories for all inputsignal statistics—a chaotic system.

Proof. First, a proof of deterministic property of the analog filter (orencoder). As in [13], mutual information between the comparator's 1-bitoutput y[n] and the analog input V_(in)[n] is defined as,I(V _(in)[n],y[n])=H(y[n]|y[n−1], . . . y[1])−H(y[n]|y[n−1], . . .y[1],V _(in)[n], . . . V _(in)[1])  (1)

Since the first term H (y[n]|y[n−1], . . . y[1]) can be at most equal to1 bit, the mutual information term is maximized if and only if thesecond term is equal to zero. The second term is zero if and only if thestate of the encoder is fully described given the input analog signal(i.e., it is not stochastic). Second, the state boundedness can beproved by contradiction. If the state is unbounded it must grow toeither positive infinite or negative infinite (not both). Otherwise, itsbandwidth would grow to infinity, which cannot be the case withdiscrete-time systems. Therefore, if the state becomes unbounded theoutput from the comparator y[n] would be a constant value that carriesno information (i.e., information rate falls below the capacity). Third,according to Theorem 3, since the state value over its trajectory musthave a delta autocorrelation function it must follow aperiodic orbits(i.e., random-like nature). Finally, if an analog encoder is to producean output that has white spectrum (aperiodic orbits) for any inputsignal statistics, it should do so even in the limiting case where theinput signal is a delta function with the maximum bandwidth of f_(s)/2.In this case, the input signal affects only the initial state of theanalog encoder and the subsequent state values continue to change ontheir own over aperiodic orbits. Therefore, it must be sensitive toinitial conditions—a “Butterfly effect”. An alternative limiting case,when the input analog signal is a DC signal, would lead to the samerequirement about the analog encoder.

Discrete-Time TurboADC: This prior-art on a discrete-time implementationof TurboADC is described in detail in [13] and it is provided here asbackground information. First, a simple discrete-time dyadictransformation (or Bernoulli map) that can give rise to chaotic behavioris considered. The phase space of this simple map is shown in FIG. 3(a),which in its original form does not allow the use of an independentvariable to affect the state's trajectory. There are several ways toensure that an input analog signal is introduced into the chaotic map toaffect the state's aperiodic trajectory. FIG. 3(b) depicts the phasespace of a modified Bernoulli chaotic map proposed in this work. Thisparticular map has been proposed for two reasons. First, it maximizesthe dynamic range and signal-to-noise ratio (SNR) by allowing theamplitude of the input signal V_(in)[n] to reach maximum level ofV_(ref). Second, it ensures a simple switched-capacitor circuitimplementation, as shown in FIG. 4. Also, Eqs. (2a)-(2e) show thedynamical law of this chaotic system, where s[n] is the internal stateof the chaotic filter and V_(ref) is the reference analog voltage usedby a TurboADC for digitization.

$\begin{matrix}{\mspace{76mu}{{q\left\lbrack {nT}_{s} \right\rbrack} = {{s\left\lbrack {nT}_{s} \right\rbrack} + {V_{in}\left\lbrack {nT}_{s} \right\rbrack}}}} & \left( {2a} \right) \\{\mspace{76mu}{{y_{0}\left\lbrack {nT}_{s} \right\rbrack} = \left\{ \begin{matrix}{\mspace{11mu}{1,}} & {{q\left\lbrack {nT}_{s} \right\rbrack} \geq 0} \\{{- 1},} & {otherwise}\end{matrix} \right.}} & \left( {2b} \right) \\{\mspace{76mu}{{y_{+}\left\lbrack {nT}_{s} \right\rbrack} = \left\{ \begin{matrix}{1,} & {{q\left\lbrack {nT}_{s} \right\rbrack} \geq V_{ref}} \\{0,} & {otherwise}\end{matrix} \right.}} & \left( {2c} \right) \\{\mspace{76mu}{{y_{-}\left\lbrack {nT}_{s} \right\rbrack} = \left\{ \begin{matrix}{{- 1},} & {{q\left\lbrack {nT}_{s} \right\rbrack} \leq {- V_{ref}}} \\{\mspace{14mu}{0,}} & {otherwise}\end{matrix} \right.}} & \left( {2d} \right) \\{{s\left\lbrack {\left( {n + 1} \right)T_{s}} \right\rbrack} = {{a \cdot {q\left\lbrack {nT}_{s} \right\rbrack}} - {V_{ref}\left( {{y_{0}\left\lbrack {nT}_{s} \right\rbrack} + {2 \cdot {y_{+}\left\lbrack {nT}_{s} \right\rbrack}} + {2 \cdot {y_{-}\left\lbrack {nT}_{s} \right\rbrack}}} \right)}}} & \left( {2e} \right)\end{matrix}$

The state s[n] remains bounded in the [−aVref, aVref) interval andtrajectory is deterministic in absence of electronic noise. For certainvalues of the gain (e.g., a=2) and initial state the map exhibits a truechaotic behavior with the Lyapunov exponent equal to log(2). A blockschematic of the described DT TurboADC based on the modified Bernoullichaotic map in Eqs. (3) is shown in FIG. 4. Since the input to theinternal quantizer is compared against three thresholds (−V_(ref), 0,V_(ref)), a 2-bit quantizer and 2-bit feedback DAC are required in thisimplementation. In a way, DT TurboADC represents a hybrid between the ΔΣmodulator and the Cyclic ADC, with the best features of bothdesigns—oversampling, noise shaping, and simplicity from the ΔΣ ADC andfast half-interval searching from Cyclic ADC. However, unlike the ΔΣmodulator that employs a DT integrator to shape the quantization noiseoutside the signal band, the DT TurboADC employs an unstable filter(pole z_(p)=2 outside the unit circle), where both signal andquantization noise are shaped over aperiodic orbits. This allows it toachieve much higher R-BW products than the discrete-time ΔΣ ADCs. Also,unlike the Cyclic ADC, where each input signal sample is converted todigital independently of other input samples, the present state of theinternal chaotic filter in TurboADC depends on the entire past of theanalog input signal. In another work described in [14], ananalog-to-digital converter is implemented as a discrete-time chaoticmap whose initial state is set equal to an input signal sample and themap is then allowed to traverse through a total of N discrete stepsgenerating output digital bits without further influence from the inputsignal. Even though the Chaotic ADC in [14] is an example of usingdiscrete-time chaotic map to convert input analog signals to digitalformat, in essence, its operation is equivalent to the well-known CyclicADC. In both Cyclic ADCs and Chaotic ADC presented in [14], the inputsignal affects only one state value (the initial state of the chaoticmap), while the electronic noise is affecting the state's trajectoryduring the entire conversion process (i.e., a random noise adds in allof the N steps required to generate N digital bits at the output)resulting in a greater sensitivity to electronic noise and largelyunfavorable signal-to-noise ratio. Unlike the Chaotic ADC in [14] andCyclic ADC, the TurboADC takes into consideration the input signal overthe entire conversion process. In addition, the Cyclic and Chaotic ADCin [14] are unable to maintain constant resolution-bandwidth productwhen the input analog signal experiences dynamic changes in itsbandwidth, as described below.

The following example emphasizes the significance of this differencebetween the Cyclic ADC and DT TurboADC. Let us assume that a Cyclic ADCis designed for a sampling rate of f_(s)=8 MHz with 4-bit resolution.For each of the input signal samples, the Cyclic ADC produces 4 bitsafter cycling through four comparisons (i.e., comparator operates atf_(c)=32 MHz), followed by resetting the internal state to a new inputsignal value. If we now assume that the actual analog signal applied tothe Cyclic ADC is bandlimited to 1 MHz (OSR=4), the best resolution thatthe Cyclic ADC can achieve in this case is 5 bits after averaging fouroriginal 4-bit samples. At the same time, if the DT TurboADC operates atthe same speed (f_(c)=32 MHz) and the input signal bandwidth is 1 MHz,the resolution will be 16 bits, which is a surprisingly significantimprovement of 11 bits over the Cyclic ADC. Additionally, the TurboADCwould require much simpler anti-aliasing filter.

Continuous-Time TurboADC (CT TurboADC): As described in thisapplication, TurboADC's can be implemented with a continuous-time (CT)chaotic circuit for the purpose of achieving significantly higherconversion rates. Continuous-time electronic circuits are typicallysignificantly faster than discrete-time counterparts, which aretypically strongly frequency compensated to avoid oscillatory andovershoot behavior at their output). Examples of CT chaotic circuits areChua circuits [15]-[17] and chaotic oscillators based on -Gm LC-tankoscillator [18]-[19]. Work in [19] demonstrates a -G_(m) LC-tankoscillator in 0.35 um BiCMOS technology exhibiting chaotic behavior upto 5 GHz. If used in a CT TurboADC, this circuit has the potential toachieve a direct RF signal conversion up to the same bandwidth. Exampleapplications that could benefit from the CT TurboADC are Bluetooth,mobile phones, personal networks, and other low-power radiocommunications as well as C-band radars for battlefield and groundsurveillance, as well as missile-control. The -G_(m) LC-tank oscillatormay be able to generate chaotic behavior in the range of tens of GHz inmore advanced technologies, [20]-[24] (e.g., for W-band radars). FIG. 5depicts one embodiment of the present invention based on a negativetransconductance (-G_(m)) LC tank oscillator. The cross-coupledtransistor pair Q₁ and Q₂, matched inductors L₁ and L₂ and varactors C₁and C₂ constitute a traditional LC-tank voltage-controlled oscillator(or VCO). The differential transistor pair Q₃ and Q₄ introducesnon-linearity required to sustain chaotic behavior through exponentialdependence of their currents to the applied base-emitter. Additionaldifferential pair Q₅ and Q₆ introduces input analog signal v_(in), intothe system affecting the state's chaotic trajectory. The output from thechaotic circuit is taken from the drain terminals of the cross-coupledpair (v_(d1) and v_(d2)) and it is fed to the comparator in FIG. 5. Thecomparator is triggered at the rate equal to f_(c) producing output bitstream (e.g., y[n]=1 if v_(d2)>v_(d1), and 0 otherwise).

If implemented in 65 nm CMOS technology, the design may achievebandwidth of 5 GHz with at least 8 bits of resolution in the basebandfor direct RF conversion of ISM band signals up to 2.54 GHz for use inBluetooth, WiFi, and other low-power short-range radio communications.To the best of our knowledge, CT TurboADC's are the first attempt toextend the Cyclic and SAR ADC's, which are always implemented withdiscrete-time switched-capacitor (or switched-current) circuits, to thecontinuous-time domain for much increased conversion speed and RBWproducts.

In another embodiment of the present invention, the CT Turbo ADC can beimplemented by using a continuous-time chaotic circuit based on,so-called, Chua-circuit, as shown in FIG. 6. Unlike in the traditionalChua-circuit, where the internal states are independent of an externaldriving signal, the internal states of the chaotic circuit in thisembodiment of the CT TurboADC (i.e., voltages on capacitors C1 and C2and current through inductor L) are continuously driven by an externallyapplied input signal V_(in)(t) through a resistive path (R₂). As theinternal states evolve over continuous-time trajectories, while drivenby an external signal V_(in)(t), the voltage on the capacitor C₂ iscompared against the threshold (e.g., zero volts) at the rate equal tof_(s) and the result of the comparison is presented as a digital bitstream y[n].

Baseband Decoding. The single-bit stream y[n] produced by the comparatorin CT TurboADC's must be decoded to produce a meaningful multi-bitrepresentation of the input analog signal V_(in)(t) in baseband.Contrary to Cyclic ADC, where there is a one-to-one correspondencebetween the amplitude bits of the input signal samples and informationbits at the output of the comparator (e.g.,V_(in)[n]≈V_(ref)(b₀2^(−N)+b₁2^((N-1))+b₂2^(−(N-2))+ . . . + b_(N-1)2⁻¹,where V_(in)[n] are the samples of a continuous-time input signalV_(in)(t) sampled at time period T_(s)=1/f_(s), V_(ref) is the referencevoltage, b_(k) are the output information bits (total of N) with b₀being the least significant bit), the CT TurboADC produces informationbits that are affected by many past input signal samples. Therefore,input signal baseband samples V_(in)[n] must be estimated from thecomparator's single-bit output stream. Unlike the ΔΣ ADC where thebaseband multi-bit input signal samples V_(in)[n] are estimated with thehelp of a linear decimation filter, the CT TurboADC is a non-linearsystem, and so the baseband signal must be estimated with the help ofnon-linear estimation methods. In one embodiment of the CT TurboADCinvention, the continuous-time state-space equations describingtrajectory of the chaotic system's state variable(s) are discretized intime to form a discrete-time model of the CT TurboADC with the samplingfrequency f_(s). Together with the output bit stream y[n] from the CTTurboADC, the discrete-time model representing the state-spacetrajectory of the continuous-time chaotic circuit is applied tonon-linear estimation methods as a prior knowledge for the purpose ofestimating multi-bit representation of the input analog signal inbaseband similar to decoding methods in Discrete-Time TurboADC's asdescribed in [12]. For example, a non-linear estimation method could beimplemented to iterate between two estimation steps as in Projectionsonto Convex Sets methods. The following illustrates the iterativeapproach to finding an estimate of the continuous-time input analogsignal V_(in)(t) applied to the CT TurboADC:

Step 1: Initiate the estimate {tilde over (V)}_(in) ^(b)[n] of lengthequal to M samples to zero or other appropriate initial value (where Mis chosen as a decoding window so that the estimate of an input analogsignal V_(in)(t) is produced in blocks of length M).

Step 2: Find an estimate {tilde over (V)}_(in) ^(a)[n] of length M ofthe continuous-time input signal V_(in)(t) closest to {tilde over(V)}_(in) ^(b) [n], e.g., in least-squares sense, such that when passedthrough the discrete-time state-space model of the CT Turbo ADC producesy^(a)[n] that is the same (or similar) as the original sequence y[n]generated by the comparator of the CT Turbo ADC and supplied to thedecoder as prior knowledge;

Step 3: Project the estimate {tilde over (V)}_(in) ^(a)[n] from Step 2to the nearest estimate {tilde over (V)}_(in) ^(b)[n] that satisfiesprior knowledge about V_(in)(t) (e.g., bandlimitation of V_(in)(t) orthat V_(in)(t) is a linear combination of known orthogonal basisfunctions).

Step 4: Repeat Steps 2 and 3 until satisfactory convergence is achieved.

In another embodiment of the present invention, the non-linear decoderof the output bit stream y[n] from the CT Turbo ADC is decoded by usinga recurrent neural network, as illustrated in FIG. 6, which is trainedon data produced by simulating the output bit stream y[n] from the CTTurbo ADC for a broad class of signals applied to the input of the CTTurbo ADC (e.g., periodic input signals such as sinusoidal signal(s),wide-band and narrow-band random signals and combination thereof).

The new class of ADCs, termed CT TurboADC, that is described above iscapable of achieving fundamental theoretical limit to theresolution-bandwidth product (or conversion capacity). The discussionabove shows that a TurboADC should employ a deterministic chaoticcircuit to achieve the capacity. A continuous-time implementation ofTurboADC with the front-end circuit complexity similar to a simple1^(st) order continuous-time ΔΣ modulator is also described. Ability tomaintain resolution in the baseband that is proportional to the OSR(defined as the ratio between one half the sampling frequency and theinput analog signal's bandwidth) surpassing all existing ADC methods,whose resolution is proportional to log₂(OSR), opening up possibilitiesfor new data conversion applications such as high-speed direct RF signalconversion in radar, high-speed communications, and medical imaging.

Although the foregoing has been described in some detail for purposes ofclarity, it will be apparent that certain changes and modifications maybe made without departing from the principles thereof. It should benoted that there are many alternative ways of implementing both theprocesses and apparatuses described herein.

Accordingly, the present embodiments are to be considered asillustrative and not restrictive, and the body of work described hereinis not to be limited to the details given herein, which may be modifiedwithin the scope and equivalents of the appended claims.

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The invention claimed is:
 1. An analog-to-digital converter (ADC),comprising: a port for an input analog signal; a source configured toprovide a continuous-time chaotic encoding signal that is deterministic,aperiodic above a threshold, and bounded; an encoder configured toencode said input analog signal with said chaotic signal to therebyproduce an encoded analog signal; a quantizing circuit configured toquantize said encoded analog signal into a bit stream; and a decoderconfigured to apply to said bit stream a non-linear estimation relatedto said chaotic signal to thereby produce an output representing saidinput analog signal in digital form; wherein aperiodic above a thresholdrefers to lacking spectral tones above a threshold.
 2. The ADC of claim1, wherein said input analog signal is sampled at an oversampling rate(OSR) and said output signal has a resolution R proportional to OSR. 3.The ADC of claim 1, wherein the output signal has a resolution R thatvaries linearly with a bandwidth BW of the ADC.
 4. The ADC of claim 1,wherein the chaotic encoding signal is generated by a chaotic oscillatorbased on negative-Gm LC-tank oscillator.
 5. The ADC of claim 1, whereinthe chaotic encoding signal is generated by a continuous-time chaoticChua circuit.
 6. The ADC of claim 1, wherein the decoder producing anoutput representing said input analog signal in digital form isimplemented as a neural-network.
 7. The ADC of claim 1, wherein: theinput analog signal is sampled at an OSR; output signal has a resolutionR that (1) is proportional to OSR; or (2) varies linearly with abandwidth BW of the ADC; the chaotic encoding signal is generated byeither (1) a chaotic oscillator based on negative-Gm LC-tank oscillator;or (2) a continuous-time chaotic Chua circuit; and, the decoderproducing an output representing said input analog signal in digitalform is implemented as a neural-network.